18-743 Project: Low Power & Energy AES Implementations

This report presents low power hardware implementations of the advanced encryption standard (AES). The low power circuit level design were implemented in a 65nm CMOS process from STMicroelectronics. A full AES model in System Verilog was written. This design was synthesized in Synopsys Design Compiler using a range of standard cell gate libraries for comparison purposes and to find the lowest power and energy configuration. The base design was synthesized with general purpose standard VT (GPSVT) gate libraries. For comparison, the gate libraries of the base design were changed to general purpose high VT (GPHVT), low power standard VT (LPSVT) and low power high VT (LPHVT) gate libraries. Further synthesis and exploration of custom implementations will be carried out, including investigating the power and area savings of ROM for the SubBytes operation.The focus of the project is on low power and energy AES-128 encryption. The keys required for the encryption will be supplied on the fly. After the synthesized and custom designs, the low power implementations will be compared to the base design implementation with respect to their performance and energy. The comparison of different low power circuit level implementations will be useful for future low power AES research and low power AES hardware implementations.